Computer Organization
Project-5: CPU Design Contest
This is a bonus project and also a design contest. For this project, you have to design a single cycle
MIPS CPU that can execute all the instructions in our previous projects and additionally jump
instruction. You will have instruction and data memories other than the registers. You will show in
the day of demo that all instructions work. You can use behavioral Verilog only for the memory
elements and testbench. Other parts must be structural. Your design will get no inputs from
outside other than the program instructions loaded into its instruction memory and will execute
the program and then we will observe the modified memory contents through simulation.
We (instructor and TA of the course) will check your projects on demo day and choose one of the
projects as the best one and this project will be graded by at least 2 extra points that will be added
to the last score collected by the student. This is an individual project and cheating will be severely
punished. By this final project you can get a total of 10 points at most that will be added your last
score in the course, which means %10 contribution.
Be ready for the demo. Your demo performance will also be graded.
Other than the demo you prepared, we can give you a program to be loaded into program memory
and we may want you to execute that program and get the perfect result.
We will help the champion to implement his/her design into an FPGA and also help him/her apply a
TUBITAK project with that design if it is worth.
On the day of the demo, we will also copy your code to test if there is any cheating.
Do your best!!
Please be sure that your design simulates correctly. Designs that are not even simulating can get at
most 15 points. Therefore at least support a subset of instructions correctly to get more points.
Be ready and well prepared for the demo.
