Assignment 8: 1. Write the Verilog code for a JK Flip-flop

Assignment 8:
1. Write the Verilog code for a JK Flip-flop using case structure and if-else statement.
Validate the result using Testbench.
2. Repeat the same problem for a Master-Slave JK flip-flop using case structure and if-else
statement. Verify again using Testbench.