P1. We know VLIW ISAs have a more difficult time finding instruction level parallelism than a superscalar machine, because of its inability to account for the dynamic behavior of the code. But suppose we know of some application (call it program A) for which VLIW machine V achieves significant speedup over your favorite superscalar machine (a 4-wide superscalar). Tell me one thing that is probably true of the program A. Tell me two things that are likely true of VLIW machine V.
P2. Consider the following loops. For each, would we expect better performance from a 4-wide in-order superscalar processor, or a scalar out-of-order processor? Assume floating point adds and subtracts have a latency of 3 cycles, integer adds and subtracts, as usual, have a latency of 1 cycle, and loads have a latency of 2 cycles.
L1: ld F7, 1000(R3)
add.d F5, F6, F7
sub.d F9, F5, F2
add.d F2, F9, F3
add.d F4, F6, F9
addi R3, R3, #4
bne R3, R12, L1
L2: add R5, R6, R8
sub R9, R5, R2
and R2, R5, R3
xor R4, R7, R9
lw R10, 1000(R5)
add R8, R10, R9
bne R4, R12, L2
P5. Are the following statements more likely to be true or false?
a. The smaller the issue width, the fewer functional units we’re likely to have.
b. The larger the number of physical (renaming) registers, the smaller the ROB size.
c. Dynamic scheduling is less critical on a superscalar machine than a scalar machine.
d. OOO superscalars are less sensitive to the quality of the branch predictor than OOO scalar processors.
