Final Project –MIPS Processor with Structural Verilog

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CSE 331 Computer Organizations
Final Project – Fall 2016
MIPS Processor with Structural Verilog

In this project you will design an improved version of the single cycle processor
shown below using structural Verilog on Altera Quartus II.
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Your design will support all core instructions of MIPS shown below:
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Rules:
1. Behavioral Verilog is NOT PERMITTED. Thus, first draw your schematic on a
paper. Only Structural Verilog is allowed. (All your Boolean expressions will
be implemented by assign, etc. But you cannot use always, if, case,
etc.)
2. Designs that are not even simulating can at most get 30pts. You get partial
grades if at least a reasonable subset of the instructions shown above can
be executed.
3. All project details will be announced at next PS (December 5). So attend
the PS for your own good! Otherwise you get no credits.
4. The input-output names must be exactly the same as explained by the
instructor during the PS.
5. You should also write Verilog testbench and simulate your design using
ModelSim. Use writememh and readmemh for instruction memory
initialization and content viewing of the memory.
6. Each day of late submission will result in 15pts reduction.
7. This project is REALLY IMPORTANT FOR YOU. So please ATTEND whatever it
takes.
8. Feel free to ask if you have any difficulty.
9. (BONUS) If you come with a solution to perform a successful demo on
Terasic DE0 board, you will get 25pts Bonus. Ask details to your TA.