EE2230 Logic Design Lab 1
Lab 1: Verilog HDL
Objective
ü Review fundamental logic components.
ü Introduce Verilog HDL modeling and verification.
Prerequisite
ü Fundamentals of logic gates and Verilog HDL.
Experiments
1 Design and implement a full adder. (s+cout=x+y+cin)
1.1 Write the logic equation.
1.2 Draw the related logic diagram.
1.3 Verilog RTL representation with verification.
2 Design a single digit decimal adder with input A(a3a2a1a0), B(b3b2b1b0), Cin(ci), and output
S(s3s2s1s0) and Cout(co).
3 (Bonus) Design a 3-to-8-line decoder with enable (input in[2:0], enable en and output
d[7:0]).
3.1 Logic equation,
3.2 Logic schematic,
3.3 Verilog RTL representation with verification.
TA:
