Project Assignment Simple Processor

CS223 Project Assignment
Simple Processor
Project Report Submission Deadline: 19

Computer Engineering Department, Bilkent University 1
For the course project, you are going to implement a simple programmable processor in
SystemVerilog. The processor will have a simple architecture but demonstrate your knowledge of
designing datapath and controller of a processor. The processor here will only support seven
instructions which are Load, Store, Add, Subtract, Ascending Sort, Descending Sort and Display.
Overall Architecture
Figure1 illustrates an example of a general-purpose processor. In the control unit, you will have
a program counter (PC) register to keep track of the next instruction that is going to be executed.
Instruction register (IR) will fetch that “next” instruction from the instruction memory. The controller
FSM will decode the instruction in the IR and send the control signals to the datapath accordingly.
There are two additional memory units to register files here, data memory and instruction memory.
Data memory is to provideadditional space for data since register files offer very limited space, and
instruction memory is where the program (instructions) to be run is stored.
Figure1. Example processor design
CS223 Project Assignment
Simple Processor
Project Report Submission Deadline: 19
th Dec 2022 – 09:00 am
Computer Engineering Department, Bilkent University 2
Building blocks
1. PC: A register that holds the address of the next instruction to be executed.
2. Instruction memory: An array of registers that stores the instructions that will be
execute.
3. Register file: An array of registers that keeps data.
4. ALU: a module that performs the arithmetic operations
5. Data memory: An array of registers that keeps data. (Additional space to store data)
Instruction Set
In the following, we define how the instructions are represented using 12-bit and what each
instruction is actually supposed to do. The processor should be able to execute seven different
types of operations: Load, Store, Sub, Add, Asc, Des and Disp. The most significant 3-bits of each
instruction are used to identify the operation type (Load, Store, Sub, Add, Asc, Des and Disp) and
the rest of the bits can be interpreted differently according to the instruction.
Load– 000 xx r2r1r0 d3d2d1d0: This instruction specifies a move of data from the data
memory location (D) whose address is specified by bits [d3d2d1d0] into the register file (RF)
whose address location is specified by the bits [r2r1r0]. For example, the instruction “000
00 001 0010” specifies a move of data memory location 0010, D[2], into register file
location 001 (or RF[1]) – In other words, that instruction represents the operation RF[1] =
D[2]. Notice that in load instructions, there are 2 redundant “don’t care” bits, so
instructions “000 00 001 0010” and “000 11 001 0010” should both do the same thing as
they only differ in those bits.
Store– 001 xx r2r1r0 d3d2d1d0: This instruction specifies a move of data in the opposite
direction as the instruction load, meaning a move of data from the register file to the data
memory. So, “001 00 001 0100” specify D[4] = RF[1]. Similar to the load instruction, the 3th
and 4th most significant bits are redundant.
Sub– 010 wa2wa1wa0 rb2rb1rb0 ra2ra1ra0: This instruction specifies a subtraction of two
register-file specified by [rb2rb1rb0] and [ra2ra1ra0], with the result stored in the register
file specified by [wa2wa1wa0]. For example, “010 010 000 001” specifies the instruction
RF[2] = RF[0] - RF[1].
CS223 Project Assignment
Simple Processor
Project Report Submission Deadline: 19
th Dec 2022 – 09:00 am
Computer Engineering Department, Bilkent University 3
Add– 011 wa2wa1wa0 rb2rb1rb0 ra2ra1ra0: This instruction specifies an addition of two
register-file specified by [rb2rb1rb0] and [ra2ra1ra0], with the result stored in the register
file specified by [wa2wa1wa0]. For example, “011 010 000 001” specifies the instruction
RF[2] = RF[0] + RF[1]. The result can overflow 4 bits. In that case you can consider only the
rightmost 4 bits of the result and discard the others.
Asc– 100 wa2wa1wa0 r2r1r0 c2c1c0: This instruction specifies the sorting of multiple
consecutive register files in ascending order. The addresses of consecutive register files to
be sorted is denoted by [r2r1r0] and [c2c1c0]. [c2c1c0] is the constant that is the number of
consecutive register files to be sorted starting from the address [r2r1r0]. The sorted values
should be stored in the consecutive register files starting from the address [wa2wa1wa0].
For example, the values stored in the register files R[2], R[3], R[4], R[5] should be sorted in
ascending order and the resulting sorted values should be written into R[0], R[1], R[2], R[3]
when the instruction is “100 000 010 100”. In case of the consecutive register files include
last register file (R[7]) but the number of specified register files is still less than the constant
value [c2c1c0], you can cut it there. This case is valid for both reading and writing. For
example, the values stored in the register files R[4], R[5], R[6], R[7] should be sorted in
ascending order and the first two of resulting sorted values should be written into R[6], R[7]
when the instruction is “100 110 100 110”.
Des– 101 wa2wa1wa0 r2r1r0 c2c1c0: This instruction is for the descending version of the
Asc instruction, refer to Asc instruction details.
Disp– 110 xxx r2r1r0 c2c1c0: This instruction is responsible for displaying the data values
stored in constant [c2c1c0] number of consecutive register-files starting from the register
file [r2r1r0].
Note: The Ascending and Descending Sorting operations must be implemented with
respect to RTL design.
There are 2 important registers in the Controller module, which are PC and IR. PC is
responsible for keeping the address of the next instruction that is going to be executed. When an
CS223 Project Assignment
Simple Processor
Project Report Submission Deadline: 19
th Dec 2022 – 09:00 am
Computer Engineering Department, Bilkent University 4
instruction is executed, PC is incremented so that it will point to the next instruction in the program
(Instruction memory). IR is the register where the instruction to be executed is fetched before being
decoded. Instruction Memory (IM) is the memory where the program in machine code is being held.
Since the instruction set consistsof 12-bit instructions, IR and Instruction Memory should also hold
12-bit values. IM should have 8 slots, therefore PC should be 3 bits (to specify the address). The
processor should also be able to take instructions from switches. Therefore we have an extra input
named isexternal. If isexternal is 1, 12 of the switches should be used to define an instruction and on
the clock edge, IR should fetch the instruction defined by switches instead of the pointed instruction
in IM. In this case, the PC shouldn't also be incremented. That is why the write-enable bit of the PC
register is isexternal invert.
Register File
The register file should have 8 slots, each holding 2’s complement signed 4-bit data. It should
have three inputs for address selection: 3-bit RF_ad1 and RF_ad2 as source register addresses and
RF_wa as destination register address. They will be used for reading or writing to memory
(depending on the enable signal). It has an enable input for write (RF_we). The write data is 2’s
complement signed 4-bit data which can be shown as RF_wd. The read data are 2’s complement
signed 4-bit data which can be shown as RF_d1 and RF_d2.
Data memory
The data memory would work just like a register file but only differ in memory size and ports.
It should have 16 slots, each holding 2’s complement signed 4-bit data. Unlike the register file, it
should only have one input for address selection, 4-bit (M_add), which will be used both for reading
and writing to memory (depending on the enable signals). It has two separate enable inputs for
write (M_we) and read (M_re). The write data is 2’s complement signed 4-bit data which can be
shown as M_wd. The read data is also 2’s complement signed 4-bit output which can be shown as
M_rd.
Controller
The controller can be modeled as a state machine with states responsible for mainly fetching
the instruction, decoding the instruction and executing the operation. In Fetch state, the next
instruction should be written to IR register. In the next clock cycle, the instruction in IR should be
CS223 Project Assignment
Simple Processor
Project Report Submission Deadline: 19
th Dec 2022 – 09:00 am
Computer Engineering Department, Bilkent University 5
decoded and next state should be determined according to the most significant 3 bits of the
instruction. In other words, according to the three most significant bits of the instruction (opcode),
we should move to one of the seven states Load, Store or Addition, Subtraction, Ascending Sorting,
Descending Sorting, and Display. And finally, after we are done with that instruction, we go back to
the Fetch state, waiting for next pushbutton press to execute the next instruction. Please note that
moving from one state to another should be synchronized by the clock signal. The important thing
about the controller of your processor is that, you should decide what set of control signals should
be enabled or disabled in either state of the controller. To make it clear for you, let’s give an
example. Assume after decoding the incoming instruction, you found out that the instruction is a
load instruction. Respectively, you will set your next state as Load state. In the Load state, in order
for your datapath to work properly, the controller should give the right values to the datapath. For
the case of Load instruction, it should set the following signal as below:
M_add =d3d2d1d0 / M_re = 1 / M_we = 0 / RF_we = 1 / RF_wa = r2r1r0
User Interface
 Left pushbutton will be used to execute the next instruction in the instruction memory.
Toavoid pressing multiple times a debouncer is needed. The processor should wait idle if
no button is pressed.
 Right pushbutton will be used to execute the instruction defined by switches. It is the signal
isexternal. Here also, a debouncer is needed.
 Middle pushbutton will be used to load the instruction that is specified by the user to the
back of the queue in the instruction memory. Here also, a debouncer is needed.
 Upper pushbutton will be used to load the data value that is specified by the user to the
register-file address that is also specified by the user. Here also, a debouncer is needed.
 Lower pushbutton will be used to clear everything existed in the processor and reset the
controller. Here also, a debouncer is needed.
 12 rightmost switches on Basys3 will be used to provide user-defined instruction.
 7 leftmost switches on Basys3 will be used to provide user-defined data value along with the
register-file address where the 4 leftmost switches correspond to the data value and the
remaining ones correspond to the register-file address. For instance, if the user inputs
0010110, RF[6] should get the decimal value 2.
CS223 Project Assignment
Simple Processor
Project Report Submission Deadline: 19
th Dec 2022 – 09:00 am
Computer Engineering Department, Bilkent University 6
 SevenSegment Display will be used for Sub, Add, Asc, Des, and Disp instructions.
o For Sub and Add instructions, the inputs A, B should be displayed in the leftmost
2 digits and the result should be displayed on the rightmost digit. The remaining
digit should be turned off.
o For Asc and Des instructions, the resulting sorted values should be displayed in
order with 1 second time periods in the rightmost digit. The constant value
should be displayed in the leftmost digit at each period. The remaining digits
should be turned off.
o For Disp instruction, the data values should be displayed with 1 second time
periods in the rightmost digit. The constant value should be displayed in the
leftmost digit at each period. The remaining digits should be turned off.
Project Report
In the project report, you need to submit the following:
a) Cover Page
b) RTL schematics for Ascending and Descending Sorting operations
c) Controller High-Level State Machine Diagram
d) Controller Block Diagram
e) Controller/Datapath Top Module Block Diagram
c) Testbenchs(Thisis optional, mainly for partial points if Basys3 doesn’t work properly)