Basic Computer Organization_lab 4

BASIC COMPUTER ORGANIZATION
1. Objectives In this laboratory, students will analyse the structure of a basic computer, will devise and design its control unit, and will use opcodes to write simple programs in machine code. The design must function in simulation, and also on the DE2-115 Altera development board. 2. Equipment and Supplies: * Quartus II (student edition or web edition) * Altera DE2-115 board with - USB-blaster cable - Power supply 12 VDC, 2A 3. References x You are provided with all the .bdf files, except one that describes the combinational circuits which generates the output and transition functions of the Control Unit and which you are expected to conceive and develop. Their logic diagrams are annexed to this document. x Chapters 5 and 6 of the textbook: Computer Systems Structures, Morris Mano, 3rd edition, 1993, ISBN 0-13-175563-3. x The course notes x The user guide of the Altera DE2-115 development kit is provided in the Laboratories Documentation section of your CEG2136 Virtual Campus.
4. The Structure of the Basic Computer 4.1 General View This laboratory implements a computer having a structure that is very close to the one presented in figure 5.4 on page 130 of your textbook. However, there are two major differences: 1. The designed computer’s memory (storing both programs and data) has a capacity of 256 words of 8 bits (256 x 8). In the textbook, the BASIC computer has a memory with words of 16 bits, each word being capable of storing one memory-reference instruction (which consists there of a 4-bit opcode and a 12-bit memory address). In this lab, a memory-reference instruction is 2 byte long as well, but the msb byte carries the opcode, while the lsb byte contains the operand address (8 bits are enough to address a memory space of 28 = 256 memory locations); as such, a 2-byte memoryreference instruction is stored in 2 consecutive memory locations (two 1-byte words). Consequently, two successive READ cycles are needed to fetch a memory-reference instruction: first to get the opcode, and the second to get the address of the data that the opcode will use. 2. The second major difference consists in the additional circuits which will allow a user to visualize the contents of the memory independently of having a program running or not on the DE2-115 board. User can preset the DIP switches on the board with the memory address to be visualized. Before the fetch phase of each instruction, the BASIC computer reads the contents of the memory location pointed at by the DIP switches on the board, and shows it in hexadecimal format on the 7 segment display of the board.
The block diagram of your computer is presented in Figure 1. The .bdf files of all the component blocks, except the Instruction Decoder (lab_controller of CU), will be provided. The Control Unit functions in accord with a time sequence which is generated by the sequence counter (SC) that plays the role of
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FSM state register. The SC initial state is 0; it restarts counting from 0 at the beginning of each instruction of a program and it is reset to 0 once that instruction is finished. A decoder converts the 4bit output of the SC into time-signals, distinct for each possible output (for example, when the SC output is 0010, then the T2 output of the decoder will go high, if not, it will remain low for any other combination); this combination of the SC and its decoder implement a One-hot encoded state register. The control commands for the Datapath are synthesized by the Instruction Decoder as (FSM output) functions in terms of the contents of the IR, DR and other signals from the Datapath; a set of gates (AND, OR, and NOT) forms the Instruction Decoder. As some CU outputs are of Mealy type, a bank of buffer registers (Control Register) is used to insure a duration of one clock period for the control commands that are generated by the CU, and to synchronize them with the system clock.
Figure 1: Computer block diagram
The following sequence of steps (grouped in 3 sets – Display, Fetch and Execution) is repeated for each instruction cycle, as long as Stop Register = 0: Display 1. The address of the memory location to being displayed (specified by the DIP switches) is loaded from register OUTA to register AR. 2. The content of memory location at this address is loaded into OUTD whose output is connected to the 7-segment display. Steps 1 and 2 are always executed, even if the system is in halt.
256x 8 Memory
Address register (AR)
Program counter (PC)
Data register (DR)
Instruction register (IR)
INPUT Address REGISTER ( OUTA)
ALU
DIP switches (addr. to display)
Stop register
Sequence counter (SC) State Register
Instruction Decoder (lab_controller)
Control Register (Register bank)
State Decoder (T)
Bus select
IR[7..0]
DR[7..0]
Control commands to counters, registers, bus multiplexer and ALU
Data[7..0]
OUTPUT Data REGISTER (OUTD) 7-segment displays 7-segment display controllers
Control Unit Datapath
Accumulator (AC)
I/O
CPU
Data[7..0]
Data[7..0]
Address [7..0]
4
16
8
8
8
8
8
8
8
8
8
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Fetch 3. The content of the Program Counter PC (containing at this point the address of the current instruction) is loaded into AR (address register). PC determines the address of the memory location from where the instruction is fetched (read) into the IR of the CPU. Since PC is reset to 0 whenever the UP2 board is programmed, your program’s first instruction has to be stored in the first memory location (address 00). 4. PC is incremented to be prepared for getting the next instruction byte. 5. The first byte of the instruction (opcode) is fetched from memory and is stored in IR (instruction register). 6. The IR content (instruction opcode) is decoded by the Instruction Decoder (in Control Unit). 7. If the instruction refers to a register, then skip to step 10. 8. If the instruction refers to memory, the PC content is transferred to AR, to get the second byte of the instruction. This second byte of the instruction may contain x either the address of the operand - if direct addressing mode; the instruction’s second byte (the operand address) is read and directly loaded into AR; x or the pointer to the operand address (i.e., address of the operand address) if indirect addressing; This pointer is read from the memory location pointed by instruction’s 2nd byte and is loaded to AR; then a newer read is performed to get the operand address and move it to AR. The FETCH cycles conclude with AR carrying the operand address. Execution 9. The data (operand) is read from the memory, and the PC is incremented to pointing to the next instruction and being prepared for the next FETCH. 10. The EXECUTION cycles of the instruction are implemented, which requires typically several more steps. 11. In the last cycle of the execution the SC is reset to 0, and the procedure begins again at step 1. NOTE: x Setting Stop Register = 1= blocks incrementing PC and stops running further instructions. These steps will be discussed in detail below. x You will use a new type of file for memory initialization (.mif), to specify the contents of memory; just go to “File” and open a “New” file which will display the list of file formats from where you should select “Memory Initialisation File.” For this lab, the file .mif has to be named memorycontents8.mif. To use hex numbers, you have to right-click on the Addr region and then choose Hexadecimal for both Address and Memory (content) Radix. Save Every time you change the contents of this file, you have to save and recompile your project. x Every time you want to run the program that you loaded in the memory, you have to reprogram your device.
4.3 Syntax of the computer instructions The instructions that can be executed by the computer are shown in Table 1. The second most significant bit (IR6) specifies if the instruction is a memory-reference instruction (IR6=0) or a registerreference instruction (IR6=1). The msb (I = IR7) specifies the instruction addressing mode (direct or indirect), while the other 6 bits form the opcode. For memory-reference instructions with direct addressing mode another memory access is needed to read the operand, while two more memory read cycles are needed to get the operand in case of indirect addressing. In conclusion, ƒ register-reference instructions are encoded with one byte: {opcode}, ƒ memory-reference instructions employ a two byte format as follows: o memory-reference instructions with direct addressing: {opcode, operand address} o memory-reference instructions in indirect addressing: {opcode, address of the operand address}.
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Table 1: Computer Instructions List
Type of Instruction Symbol
Binary opcodes = hex opcodes Description Direct Addressing I = IR7 = 0 Indirect Addressing I = IR7 = 1
Memory Reference (IR6 = 0)
AND 00 000001=01 10 000001=81 AND AC to memory word ADD 00 000010=02 10 000010=82 Add a memory word to AC SUB 00 000011=03 10 000011=83 Subtract a memory word from AC LDA 00 000100=04 10 000100=84 Load AC from a memory location STA 00 001000=08 10 001000=88 Store AC to a memory location BUN 00 010000=10 10 010000=90 Branch unconditionally ISZ 00 100000=20 10 100000=A0 Increment content of memory location and skip the following instruction if the incremented number is 0
Register Reference (IR6 = 1)
CLA 01 000001=41 Clear AC CMA 01 000010=42 Complement AC ASL 01 000100=44 Arithmetic left shift AC ASR 01 001000=48 Arithmetic right shift AC INC 01 010000=50 Increment AC HLT 01 100000=60 Halt. A Stop bit is set to 1, which prevents PC from being incremented. Now let us consider the following example file which presents a simple program in the memory (in machine code and commented with assembly language): % THE PROGRAM IS IN THE ADDRESS ZONE 00 - 7F % 00: 04; % LDA (direct) % 01: 80; % from address 80H; AC contains now the number 1AH % 02: 44; % ASL (direct); AC contains 34H now % 03: 02; % ADD (direct) % 04: 81; % add number of address 81H to AC; AC contains now 5FH% 05: 08; % STA (direct) % 06: a0; % AC sent to the address memory A0H % 07: 83; % SUB (indirect) % 08: 90; % @ address 90H is data pointer (82H); AC =5FH-65H =FAH % 09: 08; % STA (direct) % 0a: a1; % store AC to the address memory A1H % 0b: 60; % HLT % % DATA ARE IN THE ADDRESS ZONE 80 to FF % 80: 1a; 81: 2b; 82: 65; 90: 82; % address A0H is reserved for the addition result % % address A1H is reserved for the subtraction result % The hex number of the first column indicates the address in the memory, while the second hex number indicates the instruction (opcode or operand’s address) represented in machine code. The symbol % delimits the comments; these comments will contain the assembly language mnemonics of opcode of the instructions at hand (assembly language representation). From operating point of view, the memory space of our computer is divided in two: the first half (00-7F) carries the code of your program, while the second half (80-FF) is dedicated to storing data (initial operands and results). (#00) The program starts at address 00, with memory –reference instruction LDA that loads the register AC with a number which is stored at address 80H; this number is 1AH. (#02) The second program line contains a register-reference instruction, ASL, which is executed in only one reading cycle of memory. The AC contents are shifted to the left and become 34H.
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(#03) This instruction adds the number stored at address 81H to the AC, i.e., performs 34H+2BH= 5FH (#05) Next instruction stores the sum obtained in AC at address A0H. (#07) An indirect subtraction is performed here. Address 90H contains a pointer to the address 82H, where the number to being subtracted (65H) is stored. The operation is then 5FH– 65H = 0FH; (#9) The resulted difference 0FH (of AC) is stored at memory address A1H, and the program stops. Choosing addresses A0H and A1H by DIP, the numbers 5FH and FAH, respectively, can be seen on the 7-segment displays. The .mif file which represents this program in machine code (bold characters of the above example) is shown in fig. 2 as it is stored in the memory.
Figure 2: .mif file which represents the program in machine code 4.4 Detailed Description of the Control Functions (to be generated by the Control Unit) Starting from Table 1, one can observe that there are three types of distinct instructions that are encoded by the two most significant bits of the instruction register (IR): 1. indicates a direct memory-reference instruction; 2. indicates a register-reference instruction 3. indicates an indirect memory-reference instruction. The seven memory-reference instructions can be discriminated by the following control signals (note that ), employing the one-hot encoding (LDA; STA; BUN; and ISZ) and partially binary encoding (AND, ADD and SUB). 1. : AND; 2. : ADD; 3. : SUB; 4. : LDA; 5. : STA; 6. : BUN; and 7. : ISZ. 670 IRIRX 671 IRIRX 672 IRIRX 620 IRXX ? 0160 IRIRIRY 0161 IRIRIRY 0162 IRIRIRY 263 IRIRY 364 IRIRY 465 IRIRY 566 IRIRY
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These “designations” for Xi and Yj will be used in the following sections. The following three tables detail the instruction cycles; you have to read and analyse these tables attentively and make sure that you understand each step. These tables represent the specifications for the design of the CPU Control Unit. The ALU functions are described in TABLE 5. Please note that ƒ register-reference instructions require one memory read cycle (to get the opcode in T3), ƒ memory-reference instructions in direct addressing mode need three memory read cycles: o 2 read cycles to fetch the instruction (one for the opcode in T3 and another one for the operand address in T6), and o a third cycle to get the operand in T8 to execute the instruction, ƒ memory-reference instructions in indirect addressing mode need four memory read cycles (3 read cycles to fetch the instruction – the 1st cycle to read the opcode in T3, the 2nd cycle to read the address of the operand address in T6, the 3rd to get the operand address in T7, and the 4th cycle to get the operand in T8). Table 2: Instruction Fetch Cycle (Initialisation) - common to all types of instruction State Description Notation RTL T0 Load the address register AR with the contents of OUTA T0: AR ← OUTA T1 Read memory location pointed to by AR to the data output register OUTD T1: OUTD ← M [AR] T2 ƒ Load AR register with the ADDRESS of the opcode of the current instruction (PC) ƒ Increment PC (if the program is running, i.e., if Stop FF S = 0) to point to the address of the next byte to be read, which can be: o the next instruction, if the current instruction is a register-reference instruction o the 2nd byte of the current instruction, if it is a memory-reference instruction. T2: AR ← PC T2S’: PC ← PC + 1 T3 Read the instruction’s first byte (opcode) from memory location specified by AR to IR T3 : IR ← M [AR] T4 This state is a delay that allows the opcode to be decoded in the Control Unit. (nothing) T5 If , the byte in IR is a register - reference instruction and will be executed now T5X1: execute instruction from Table 3 T5X1 :SC ← 0 If or ( memory - reference instruction), ƒ PC is copied to AR, i.e, the address of the instruction’s 2nd byte goes from PC to AR = now AR contains the ADDRESS of o the operand address if direct addressing, or o the address of the operand address if indirect addressing ƒ Increment PC if the program is running (Stop FF S=0). Note that . T5IR’6 : AR ← PC TsIR’6 S’: PC ← PC + 1 T6 Read from memory location pointed to by AR to AR; the read byte is ƒ the operand address, if direct addressing, or ƒ the address of the operand address, if indirect addressing T6IR’6 : AR ← M [AR] T7 If indirect addressing, read the operand address from memory location pointed to by AR If direct addressing, don’t do anything, as the operand’s address is already in AR since T6 (nothing) T8 & after Execute the memory - reference instruction as described in Table 4. (see Table 4) 1X 0X 2 X ? ? 6 20 IR XX ? @ ARMARXT m:27 :07 XT
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Table 3: Instruction Execution Cycle - Control of the register - reference instructions Symbol RTL Notation CLA CMA ASL ASR INC HLT
Table 4: Instruction Execution Cycle - Control of the memory - reference instructions Symbol RTL Notation AND
ADD
SUB
LDA
STA
(cycle not allocated to allow the address bus to stabilize)
BUN ISZ (assuming that the next instruction is a memoryreference instruction, stored at 2 memory location further down)
Table 5: ALU operations table S2 S1 S0 Operation Description 0 0 0 AC + DR Addition 0 0 1 AC + DR’ + 1 Subtraction: AC - DR 0 1 0 ashl AC AC arithmetic left shift 0 1 1 ashr AC AC arithmetic right shift 1 0 0 AC š DR logic AND 1 0 1 AC › DR logic OR 1 1 0 DR DR transfer 1 1 1 AC’ Complement AC
0 :015 mACIRXT ACACIRXT m :115 ACACIRXT ashl :215 m ACACIRXT ashr :315 m 1 :415 ?m ACACIRXT 1 :515 mSIRXT
@ 0,: :
09
08
mšm m SCDRACACYT ARMDRYT @ 0,: : 19 18 m?m m SCDRACACYT ARMDRYT @ 0,: : 29 28 m?m m SCDRACACYT ARMDRYT @ 0,: : 39 38 mm m SCDRACYT ARMDRYT :8T @ 0 ,:49 m m SC ACARMYT 0,:58 mm SCARPCYT @
@ ???? ?? 0,1: alors )0( si : 1: alors 0 si: : 1: : 612 611 610 69 68 m?m ?m m ?m m SCPCPCSDRYT PCPCSDRYT DRARMYT DRDRYT ARMDRYT
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To illustrate the computer’s operation, let’s track the registers contents as the following memory – reference instruction is run:
00: ADD 80H 02: …
This translates into the machine code stored in the computer’s memory as follows
Addr Content 00: 02 01: 80 02: … State PC AR IR DR AC SC+ RTL 00 0 0 1 00 0 0 2
01 PC++
(PC) = 00 = ADDRESS of the opcode 0 0 3
01 00 = ADDRESS of the opcode
M[AR=0] = 02 =opcode
0 0 4
01 0 0 5
02 PC++
(PC) = 01 = ADDRESS of the 2nd byte of the memory-reference instruction (operand address)
opcode= 02 0 0 6
02
M[AR=01] = 80 operand address as direct addressing (not the address of the operand address since it is not indirect addressing)
opcode = 02 0 0 7 02 * M[AR] = operand address if indirect addressing (not here) opcode 0 0 8 * still the operand address as direct addressing (read in T6) = 02 (nothing) T8 02 operand address opcode = 02 M[AR=80] = operand 0 9 DR <- M[AR] T9 02 operand address 0 + operand 0 AC <- AC+DR SC <-0

0T 1T 2T
1:
:
2
2
?m m PCPCST PCART 3T @ ARMIRT m:3
4T 5T PC ARIRT m :65 1:65 ?m PCPCSIRT 6T @ ARMARIRT m:66
7T
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5. Prelab - Hardware 5.1 Files Analysis You will start up by analyzing the files .bdf which you are provided with. You can do it either by using Quartus II, or by “deciphering” the diagrams at the end of this document (Fig. 3 - 11). You don’t have to understand in detail the RAM operation (ram256x8), nor the controller of the 7-segment display. The diagram of the 4 bit SC counter is not included in the figures below, because the counter has the same architecture like the 8 bit counter, but truncated to 4 bits. Finally, the VHDL code of the bus multiplexer is presented in Table 7. Although you did not learn VHDL yet, you will see that the code is easy to understand, and much simpler to implement than would be a .bdf.
Examining the logic diagrams, answer the following questions and write your answers in your report: 1. Draw a diagram which shows the hierarchy of the files, with lab3top at the top. For the files lab3controller, ram256x8, and sevensegcontroller, you do not have to identify the subfiles. 2. How can you check by analysing these files that only one register will place its output on the data bus at a time? 3. Are the register reset (clear) signals synchronous or asynchronous? Explain your answer. Note that all the command signals are active at high (i.e. a “1” will reset a register to 0). 4. What happens if a load and a reset are simultaneously sent to a register? Why? 5. Why the address register is connected directly to the memory? 6. Why the Program Counter, the Data Register, and the Accumulator are implemented as counters? 7. Of all the three commands of the counters (reset, increment, and load), which one has the highest priority? Which one has the lowest priority? Explain your answer. 8. Is it possible to read a value from memory directly to the accumulator? Explain your answer. 9. Analyze the ALU and determine a truth table which describes the 8 operations which can be selected by the three control lines. Are the shift operations logical or arithmetic? 5.2 Design of the Control Unit Your main objective is to derive the equations of all the control signals which have to be generated by the Control Unit in order to control the CPU datapath (registers and ALU), the bus and the memory. To this effect, analyze the RTL expressions of Table 2, Table 3, Table 4, and write the logic expression for each of the following control signal (O and G functions of the Control Unit): Memory (OM(In, T)) 1. memwrite CPU registers (OR(In, T)) 2. AR_Load 3. PC_Load 4. PC_Inc 5. DR_Load 6. DR_Inc 7. IR_Load 8. AC_Clear 9. AC_Load 10. AC_Inc 11. OUTD_Load CPU ALU (OALU(In, T)) 12. ALU_Sel2 13. ALU_Sel1 14. ALU_Sel0 Bus (data mux (OBus(In, T)) 15. BusSel2 16. BusSel1 17. BusSel0 Control Unit (G(In, T)) 18. SC_Clear 19. Halt
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The inputs (In) of the Control Unit are: the Instruction Register IR [7..0], the Data Register DR [7..0], the State Register (SC) T[12..0], and the stop command (Stop) of the Stop register. The Xi and Yj functions (as described in section 4.3) are the core of the Instruction Decoder and have to be implemented first, to allow for deriving all the control signal (CU’s O and G functions) from them. To this effect, examine the tables and determine which signals must be activated to execute each RTL line. For each control signal, derive a list of the conditions under which that signal is activate. After making up the list for a particular signal, you can simply do an OR of each condition/term to obtain the final expression of that control signal. For example, let consider the bus (multiplexer) for which three select lines (BusSel [2..0]) have to be derived (OBus(In, T)). Let synthesize in a table all the conditions under which each register places its output onto the bus: Circuit which writes on the bus Control Conditions (In, T) Bus select = OBus(In, T) BusSel2 BusSel1 BusSel1
Memory 0 0 0
AR 0 0 1 PC 0 1 0 DR 0 1 1 IR (never happens here) 1 0 0 AC 1 0 1 OUTA 1 1 0 (not used) (indifferent) 1 1 1 From this table, one can see that . Actually you have to design an encoder that generates BusSel [2..0] in terms of the Control Conditions. Similar Boolean expressions have to be derived for all the other control signals. To eliminate the dependence of the duration of the output functions O(In, T) and transition functions G(In, T) to the input signals, every function is sampled and stored in a buffer synchronously with the system clock. It is worth to pay great attention when you derive your lists! 6. Procedure - Hardware
6.1 Build and test the Control Unit 6.1.1 Automatic run 1. Create a new Quartus II Project and name it appropriately with File - New Project Wizard or File-New-New Quartus II Project Add support files (both .bdf and .vhd) to project: Project-Add/Remove Files from Project Set lab3top.bdf as the top-level entity. 2. Open the file lab3controller.bdf (which gives the list of the pins of the inputs and outputs in the order required for generating by default the same symbol as shown in the file lab3top.bdf). Use AND, OR and NOT gates to implement the Boolean expressions that you derived in the prelab for the control signals (section 5.3). It is a good idea to make virtual connections by giving names to wires (simply click on a wire and enter the name; the wires which have the same
?? 632108 27 66
3 1
YYYYYT XT IRT T T ????
58 YT
5 2 T T
610 YT
49 YT 0T
4902 YTTBusSel ?
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names are automatically connected by the compiler). If you do not use virtual connections, your file will quickly become an incomprehensible set of spaghetti. Try to reduce the number of logic gates that a signal must go through. The clock period of the DE2-115 board is only 20 ns, and errors can occur if signals are delayed over this period. 3. Create your Memory Initialization File (memorycontents8.mif): File-New-Memory Initialization File; Select your radix etc... Hexadecimal. You can either put your test program into the *.mif (like the one in Fig. 2) now or later. Save the file. 4. Set lab3controller.bdf as Top-Level Entity and make sure that it compiles without errors. 5. Assign lab3top.bdf to the project (set as Top-Level Entity), and choose the device EP4CE115F29C7. Assign the pins as shown in Table 6. (right-click on pin - Locate - Locate in Assignment Editor and then switch in the Category panel from All to Locations-Pins to select the pin in the Edit panel, in the Location tab, etc… Table 6: Pins Assignment Pin Name Pin Number Component Pin Name Pin Number Component clk PIN_Y2 50MHz clock A1 PIN_M24 HEX0[0] Auto PIN_Y23 SW[17] B1 PIN_Y22 HEX0[1] DIP7 PIN_AB26 SW[7] C1 PIN_W21 HEX0[2] DIP6 PIN_AD26 SW[6] D1 PIN_W22 HEX0[3] DIP5 PIN_AC26 SW[5] E1 PIN_W25 HEX0[4] DIP4 PIN_AB27 SW[4] F1 PIN_U23 HEX0[5] DIP3 PIN_AD27 SW[3] G1 PIN_U24 HEX0[6] DIP2 PIN_AC27 SW[2] A2 PIN_G18 HEX1[0] DIP1 PIN_AC28 SW[1] B2 PIN_F22 HEX1[1] DIP0 PIN_AB28 SW[0] C2 PIN_E17 HEX1[2] 1_instruction PIN_M23 KEY[0] D2 PIN_L26 HEX1[3] AR[0] PIN_G19 LEDR[0] E2 PIN_L25 HEX1[4] AR[1] PIN_F19 LEDR[1] F2 PIN_J22 HEX1[5] AR[2] PIN_E19 LEDR[2] G2 PIN_H22 HEX1[6] AR[3] PIN_F21 LEDR[3] AC[0] PIN_E21 LEDG[0] AR[4] PIN_F18 LEDR[4] AC[1] PIN_E22 LEDG[1] AR[5] PIN_E18 LEDR[5] AC[2] PIN_E25 LEDG[2] AR[6] PIN_J19 LEDR[6] AC[3] PIN_E24 LEDG[3] AR[7] PIN_H19 LEDR[7] AC[4] PIN_H21 LEDG[4] DR[0] PIN_J15 LEDR[10] AC[5] PIN_G20 LEDG[5] DR[1] PIN_H16 LEDR[11] AC[6] PIN_G22 LEDG[6] DR[2] PIN_J16 LEDR[12] AC[7] PIN_G21 LEDG[7] DR[3] PIN_H17 LEDR[13] Stop PIN_F17 LEDG[8] DR[4] PIN_F15 LEDR[14] DR[5] PIN_G15 LEDR[15] DR[6] PIN_G16 LEDR[16] DR[7] PIN_H15 LEDR[17] Compile your project. 6. To test and visualise the simulation of your project, create a new .vwf file called lab3top.vwf. Choose a grid size of 20 ns and an end of simulation of 5μs. Make a right click and select “Insert” then “Insert Node or Bus…” and then click on “node finder” and on “List” selecting Pins: all for Filter, and Named “*”. In the panel Nodes Found select clk, DIP [7..0], etc. 7. Set the DIP switches to point to the A0 address. Also make sure the Auto signal is set to 1. Start simulation. If your Control Unit functions correctly, the register OUTD would have at the end
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the value 5F, and the Stop bit should be activated after approximately 2.7 μs. If you start again your simulation with DIP [7..0] set to A1, the register OUTD should finally contain FA. Show this simulation to your TA. 6.1.2 Manual run 8. If your simulation does not function, you have to find the source of the problem. Run short test programs (a couple of instructions) to verify the correct generation of the control signals. To help debug the issue, set the Auto signal to 0. Setting the Auto signal to 0 enables you to stepthrough the instructions (a push-button press 1_instruction, permits the user to execute the next instruction) and see where the issue is. In addition, the outputs to the following registers are displayed as well: AR, DR and the Accumulator. Check the sequence of the control signals to see whether they correspond to the order described in tables 2 - 4. Keep in mind that the signals arrive one clock cycle after the sequence counter, as they are stored first in the control registers. Another good technique of checking is to observe what is stored in the memory. Examine the signals on the data and address buses each time the signal memwrite is requested; this should help you to find out where your program causes an error. 9. Program the DE2-115 board by opening the programmer and choose “Program”. Use the DIP switches to choose the addresses for the data. 10. Enter the program of Section 4.3 in memorycontents8.mif. Program the device and use the DIP switches to read the memory content. Was your analysis of the program correct? Demonstrate to your TA.